Compartir
A Systolic Array Optimizing Compiler (en Inglés)
Monica S. Lam
(Autor)
·
Springer
· Tapa Blanda
A Systolic Array Optimizing Compiler (en Inglés) - Lam, Monica S.
$ 198.18
$ 275.25
Ahorras: $ 77.07
Elige la lista en la que quieres agregar tu producto o crea una nueva lista
✓ Producto agregado correctamente a la lista de deseos.
Ir a Mis Listas
Origen: Estados Unidos
(Costos de importación incluídos en el precio)
Se enviará desde nuestra bodega entre el
Viernes 19 de Julio y el
Viernes 26 de Julio.
Lo recibirás en cualquier lugar de Internacional entre 1 y 3 días hábiles luego del envío.
Reseña del libro "A Systolic Array Optimizing Compiler (en Inglés)"
This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu- tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
Todos los libros de nuestro catálogo son Originales.
El libro está escrito en Inglés.
La encuadernación de esta edición es Tapa Blanda.
✓ Producto agregado correctamente al carro, Ir a Pagar.