Compartir
high level synthesis of asics under timing and synchronization constraints (en Inglés)
Giovanni Demicheli
(Autor)
·
David C. Ku
(Autor)
·
Springer
· Tapa Blanda
high level synthesis of asics under timing and synchronization constraints (en Inglés) - Ku, David C. ; Demicheli, Giovanni
$ 301.31
$ 418.48
Ahorras: $ 117.17
Elige la lista en la que quieres agregar tu producto o crea una nueva lista
✓ Producto agregado correctamente a la lista de deseos.
Ir a Mis Listas
Origen: Estados Unidos
(Costos de importación incluídos en el precio)
Se enviará desde nuestra bodega entre el
Viernes 26 de Julio y el
Viernes 02 de Agosto.
Lo recibirás en cualquier lugar de Internacional entre 1 y 3 días hábiles luego del envío.
Reseña del libro "high level synthesis of asics under timing and synchronization constraints (en Inglés)"
Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
Todos los libros de nuestro catálogo son Originales.
El libro está escrito en Inglés.
La encuadernación de esta edición es Tapa Blanda.
✓ Producto agregado correctamente al carro, Ir a Pagar.
